Classic Timing Analyzer report for ProjetoSD
Fri Oct 14 13:19:00 2011
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 10.039 ns   ; A[1] ; S[3] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;      ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------+
; tpd                                                           ;
+-------+-------------------+-----------------+------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To       ;
+-------+-------------------+-----------------+------+----------+
; N/A   ; None              ; 10.039 ns       ; A[1] ; S[3]     ;
; N/A   ; None              ; 9.997 ns        ; B[1] ; S[3]     ;
; N/A   ; None              ; 9.942 ns        ; A[0] ; S[3]     ;
; N/A   ; None              ; 9.879 ns        ; B[0] ; S[3]     ;
; N/A   ; None              ; 9.759 ns        ; A[1] ; S[2]     ;
; N/A   ; None              ; 9.717 ns        ; B[1] ; S[2]     ;
; N/A   ; None              ; 9.662 ns        ; A[0] ; S[2]     ;
; N/A   ; None              ; 9.599 ns        ; B[0] ; S[2]     ;
; N/A   ; None              ; 9.579 ns        ; B[3] ; S[3]     ;
; N/A   ; None              ; 9.576 ns        ; A[3] ; S[3]     ;
; N/A   ; None              ; 9.506 ns        ; A[1] ; Overflow ;
; N/A   ; None              ; 9.464 ns        ; B[1] ; Overflow ;
; N/A   ; None              ; 9.409 ns        ; A[0] ; Overflow ;
; N/A   ; None              ; 9.365 ns        ; B[2] ; S[3]     ;
; N/A   ; None              ; 9.346 ns        ; B[0] ; Overflow ;
; N/A   ; None              ; 9.259 ns        ; A[1] ; S[1]     ;
; N/A   ; None              ; 9.251 ns        ; B[1] ; S[1]     ;
; N/A   ; None              ; 9.240 ns        ; A[2] ; S[3]     ;
; N/A   ; None              ; 9.195 ns        ; A[0] ; S[1]     ;
; N/A   ; None              ; 9.133 ns        ; B[0] ; S[1]     ;
; N/A   ; None              ; 9.097 ns        ; A[0] ; S[0]     ;
; N/A   ; None              ; 9.050 ns        ; B[2] ; S[2]     ;
; N/A   ; None              ; 9.042 ns        ; A[3] ; Overflow ;
; N/A   ; None              ; 9.038 ns        ; B[3] ; Overflow ;
; N/A   ; None              ; 8.990 ns        ; B[2] ; Overflow ;
; N/A   ; None              ; 8.960 ns        ; A[2] ; S[2]     ;
; N/A   ; None              ; 8.909 ns        ; B[0] ; S[0]     ;
; N/A   ; None              ; 8.544 ns        ; A[2] ; Overflow ;
+-------+-------------------+-----------------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Fri Oct 14 13:18:56 2011
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ProjetoSD -c ProjetoSD --timing_analysis_only
Info: Longest tpd from source pin "A[1]" to destination pin "S[3]" is 10.039 ns
    Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_AA18; Fanout = 2; PIN Node = 'A[1]'
    Info: 2: + IC(4.456 ns) + CELL(0.228 ns) = 5.541 ns; Loc. = LCCOMB_X9_Y14_N0; Fanout = 3; COMB Node = 'soma_oneBit:inst7|inst10~6'
    Info: 3: + IC(0.253 ns) + CELL(0.346 ns) = 6.140 ns; Loc. = LCCOMB_X9_Y14_N8; Fanout = 1; COMB Node = 'soma_oneBit:inst|inst4'
    Info: 4: + IC(1.795 ns) + CELL(2.104 ns) = 10.039 ns; Loc. = PIN_K7; Fanout = 0; PIN Node = 'S[3]'
    Info: Total cell delay = 3.535 ns ( 35.21 % )
    Info: Total interconnect delay = 6.504 ns ( 64.79 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 159 megabytes
    Info: Processing ended: Fri Oct 14 13:19:00 2011
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:01


