============================================================ Generated by: Encounter(R) RTL Compiler v07.10-s009_1 Generated on: Dec 23 2008 01:01:56 PM Module: uartproto Technology library: c35_CORELIB 2.0 Operating conditions: _nominal_ (balanced_tree) Wireload mode: enclosed ============================================================ Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps) ------------------------------------------------------------ (clock my_clock) launch 5000 R baudgen dl_reg[1]/C 100 5000 R dl_reg[1]/Q DFEC1 3 52.5 775 +759 5759 R g6485/A +0 5759 g6485/Q NOR21 2 40.3 500 +308 6066 F g6467/A +0 6067 g6467/CO ADD22 2 40.3 257 +400 6467 F g6448/A +0 6467 g6448/Q NAND22 2 33.3 358 +180 6647 R g6445/B +0 6647 g6445/Q NOR21 2 40.3 500 +227 6874 F g6432/A +0 6874 g6432/CO ADD22 2 40.3 257 +400 7274 F g6429/A +0 7274 g6429/Q NAND22 2 33.3 358 +180 7454 R g6426/B +0 7454 g6426/Q NOR21 2 40.3 500 +227 7681 F g6418/A +0 7681 g6418/CO ADD22 2 40.3 257 +400 8082 F g6415/A +0 8082 g6415/Q NAND22 2 33.3 358 +180 8261 R g6412/B +0 8262 g6412/Q NOR21 2 40.3 502 +227 8488 F g6406/A +0 8488 g6406/CO ADD22 1 23.2 194 +358 8847 F g6404/A +0 8847 g6404/Q XOR21 1 20.2 266 +328 9175 F dlc_reg[15]/SD TFSEC1 +0 9175 dlc_reg[15]/C setup 100 +122 9298 R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock my_clock) capture 15000 R ------------------------------------------------------------ Cost Group : 'my_clock' (path_group 'my_clock') Timing slack : 5702ps Start-point : baudgen/dl_reg[1]/C End-point : baudgen/dlc_reg[15]/SD