============================================================ Generated by: Encounter(R) RTL Compiler v07.10-s009_1 Generated on: Dec 11 2008 03:36:56 PM Module: uartproto Technology library: c35_CORELIB 2.0 Operating conditions: _nominal_ (balanced_tree) Wireload mode: enclosed ============================================================ Timing ------ Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'uartproto'. Slack Endpoint Cost Group ---------------------------------------------- +2389ps baudgen/dlc_reg[15]/D my_clock Area ---- Instance Cells Cell Area Net Area Wireload ----------------------------------------------------- uartproto 493 68032 9486 10k (S) (S) = wireload was automatically selected Design Rule Check ----------------- Max_transition design rule: no violations. Max_capacitance design rule (violation total = 46873.8) Worst violator: Pin Load (ff) Max Violation ----------------------------------------------------- g10839/Q 10008.2 4800.0 5208.2 ============================================================ Generated by: Encounter(R) RTL Compiler v07.10-s009_1 Generated on: Dec 11 2008 03:38:39 PM Module: uartproto Technology library: c35_CORELIB 2.0 Operating conditions: _nominal_ (balanced_tree) Wireload mode: enclosed ============================================================ Timing ------ Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'uartproto'. Slack Endpoint Cost Group ---------------------------------------------- +2389ps baudgen/dlc_reg[15]/D my_clock Area ---- Instance Cells Cell Area Net Area Wireload ----------------------------------------------------- uartproto 495 68978 9531 10k (S) (S) = wireload was automatically selected Design Rule Check ----------------- Max_transition design rule: no violations. Max_capacitance design rule (violation total = 46873.8) Worst violator: Pin Load (ff) Max Violation ----------------------------------------------------- g10827/Q 10008.2 4800.0 5208.2 ============================================================ Generated by: Encounter(R) RTL Compiler v07.10-s009_1 Generated on: Dec 11 2008 03:41:06 PM Module: uartproto Technology library: c35_CORELIB 2.0 Operating conditions: _nominal_ (balanced_tree) Wireload mode: enclosed ============================================================ Timing ------ Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'uartproto'. Slack Endpoint Cost Group ---------------------------------------------- +2389ps baudgen/dlc_reg[15]/D my_clock Area ---- Instance Cells Cell Area Net Area Wireload ----------------------------------------------------- uartproto 498 69087 9558 10k (S) (S) = wireload was automatically selected Design Rule Check ----------------- Max_transition design rule (violation total = 6510) Worst violator: Pin Slew (ps) Max Violation ----------------------------------------------------- g10812/Q 4380 4000 380 Max_capacitance design rule (violation total = 46880.6) Worst violator: Pin Load (ff) Max Violation ----------------------------------------------------- g10827/Q 10008.2 4800.0 5208.2 ============================================================ Generated by: Encounter(R) RTL Compiler v07.10-s009_1 Generated on: Dec 11 2008 03:43:43 PM Module: uartproto Technology library: c35_CORELIB 2.0 Operating conditions: _nominal_ (balanced_tree) Wireload mode: enclosed ============================================================ Timing ------ Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'uartproto'. Slack Endpoint Cost Group ----------------------------------------------- +5744ps baudgen/dlc_reg[15]/SD my_clock Area ---- Instance Cells Cell Area Net Area Wireload ----------------------------------------------------- uartproto 520 69997 10233 10k (S) (S) = wireload was automatically selected Design Rule Check ----------------- Max_transition design rule: no violations. Max_capacitance design rule (violation total = 46873.8) Worst violator: Pin Load (ff) Max Violation ----------------------------------------------------- g7468/Q 10008.2 4800.0 5208.2 ============================================================ Generated by: Encounter(R) RTL Compiler v07.10-s009_1 Generated on: Dec 11 2008 03:45:42 PM Module: uartproto Technology library: c35_CORELIB 2.0 Operating conditions: _nominal_ (balanced_tree) Wireload mode: enclosed ============================================================ Timing ------ Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'uartproto'. Slack Endpoint Cost Group ---------------------------------------------- +2389ps baudgen/dlc_reg[15]/D my_clock Area ---- Instance Cells Cell Area Net Area Wireload ----------------------------------------------------- uartproto 503 68286 9738 10k (S) (S) = wireload was automatically selected Design Rule Check ----------------- Max_transition design rule: no violations. Max_capacitance design rule (violation total = 46873.8) Worst violator: Pin Load (ff) Max Violation ----------------------------------------------------- g7536/Q 10008.2 4800.0 5208.2 ============================================================ Generated by: Encounter(R) RTL Compiler v07.10-s009_1 Generated on: Dec 11 2008 03:48:27 PM Module: uartproto Technology library: c35_CORELIB 2.0 Operating conditions: _nominal_ (balanced_tree) Wireload mode: enclosed ============================================================ Timing ------ Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'uartproto'. Slack Endpoint Cost Group ---------------------------------------------- +2389ps baudgen/dlc_reg[15]/D my_clock Area ---- Instance Cells Cell Area Net Area Wireload ----------------------------------------------------- uartproto 503 68286 9738 10k (S) (S) = wireload was automatically selected Design Rule Check ----------------- Max_transition design rule: no violations. Max_capacitance design rule (violation total = 46873.8) Worst violator: Pin Load (ff) Max Violation ----------------------------------------------------- g7536/Q 10008.2 4800.0 5208.2