============================================================
  Generated by:           Encounter(R) RTL Compiler v07.10-s009_1
  Generated on:           Dec 11 2008  03:03:54 PM
  Module:                 uartproto
  Technology library:     c35_CORELIB 2.0
  Operating conditions:   _nominal_ (balanced_tree)
  Wireload mode:          enclosed
============================================================

	Timing
	------
Warning : Possible timing problems have been detected in this design. [TIM-11]
        : The design is 'uartproto'.

 Slack         Endpoint        Cost Group 
-----------------------------------------------
+3913ps baudgen/dlc_reg[15]/SD my_clock   


	Area
	----

 Instance  Cells  Cell Area  Net Area   Wireload     
-----------------------------------------------------
uartproto    629      78133     11601        10k (S) 

 (S) = wireload was automatically selected

	Design Rule Check
	-----------------

Max_transition design rule: no violations.

Max_capacitance design rule (violation total = 81113.8)
Worst violator:
Pin                 Load (ff)           Max     Violation
---------------------------------------------------------
saida_reg[7]/Q        10008.2         960.0        9048.2