SBCCI 2004

17th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN
CHIP ON THE REEFS

Porto de Galinhas, Pernambuco, Brazil
September 7-11, 2004

XILINX STUDENT CONTEST

RULES AND REGULATIONS

 

Default Options:

 

In Synthesis

    Properties: click Default button on all tabs (Synthesis Options, HDL Options, Xilinx Specific Options)

In Implement Design

    Properties: click Default button on all tabs (Translate Properties, Map Properties, Place & Route Properties, Incremental Design Properties, Simulation Model Properties, Post-Place & Route Static Timing Report Properties, Post-Map Static Timing Report Properties)

If the Default button on a tab is already shaded (not accessible), it means that the Default option is already set up. No action is required.